Southwest University of Science and Technology · Electronic Information Engineering (Honors) · B.Eng.
2026.09 – 2029.06 (expected) · Mianyang, China
Transferred from Pharmaceutical Engineering in September 2026; currently in the second year. This semester: complex functions and integral transforms, probability and statistics, analog electronics, university physics, Japanese and software technology fundamentals. The electronics core — digital electronics, signals and systems — follows in later semesters.
Southwest University of Science and Technology · Pharmaceutical Engineering · first year
2025.09 – 2026.09 · Mianyang, China
Comprehensive evaluation 99.81 / 100 Top 12% of major 1st in innovation credits No failed coursesFirst-year comprehensive evaluation 99.81, ranked 7th in the major (top 12%) with the highest innovation-credit score in the major. Selected course results: Programming Fundamentals (Python) 100, Fundamentals and Applications of AI 87, Calculus B1 88, Japanese 88 / 87. Also passed the National Computer Rank Examination (Level 2) and CJT4.
Medical imaging · algorithms and software implementation
2026.04 – present
- Breast ultrasound benign/malignant classification and diagnosis support: binary classification trained on BUS-BRA and externally validated on BUSI; implemented the CNN training and evaluation pipeline, fixed the metrics and threshold policy, and produced Grad-CAM attention visualisations
- Provincial undergraduate innovation training project: interpretable pulmonary nodule classification and malignancy risk grading from chest CT; data processing and model experiments with fixed splits, seeds and evaluation scripts
- Fluorescence-guided osteomyelitis imaging software system: independently implemented the physician workstation prototype and the algorithm side, covering image review, lesion annotation and 3D display, with GPU-accelerated and CPU-fallback release configurations
"One Student One Chip" study group · RISC-V and digital design
2025.10 – present
Studying Verilog and RISC-V processor design from digital logic fundamentals, currently at the E5 stage of RTL simulation.